The present invention relates to a process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), and more particularly to a simplified back-channel-etch (BCE) process for forming the TFT matrix with reduced masking steps.
For conventional manufacturing processes of a TFTLCD, six to nine masking steps are required for forming the TFT matrix. One of the processes,.which is a 6-mask one, is illustrated as follows.
The conventional process includes steps of:
i) applying a first conductive layer onto a glass substrate 10, and using a first photo-masking and lithography procedure to pattern and etch the first conductive layer to form an active region 12 consisting of a scan line and a gate electrode of a TFT unit, as shown in FIG. 1A;
ii) sequentially forming an insulation layer 14, an amorphous silicon (a-Si) layer 16, an n+ amorphous silicon layer 18 and a photoresist 19 on the resulting structure of FIG. 1A, as shown in FIG. 1B, and exposing the resulting structure from the back side of the substrate, as indicated by arrows, wherein a portion of the photoresist 19 above the region 12 is shielded by the region 12 from exposure so as to exhibit a self-aligned effect;
iii) etching off the exposed photoresist 19, portions of the layers 16 and 18 thereunder, and the remaining photoresist so that each of the remaining layers 16 and 18 has a shape substantially identical to the region 12, and using a second photo-masking and lithography procedure to pattern and etch the layers 16 and 18 again to isolate the TFT unit 11, as shown in FIG. 1C;
iv) using a third photo-masking and lithography procedure to further pattern and etch the layers 16 and 18 to form a tape automated bonding (TAB) contact window for the scan line (not shown);
v) applying an indium tin oxide (ITO) layer on the resulting structure of FIG. 1C, and using a fourth photo-masking and lithography procedure to pattern and etch the ITO layer to form a pixel electrode 20 by a single side of the TFT unit 11, as shown in FIG. 1D;
vi) applying a second conductive layer on the resulting structure of FIG. 1D, using a fifth photo-masking and lithography procedure to pattern and etch the second conductive layer to integrally form a data line 23, a first connection line 22a between the TFT unit 11 and the data line 23, and a second connection line 22b between the TFT unit 11 and the pixel electrode 20, and using the remaining second conductive layer as a shield to etch off a portion of the doped a-Si layer 18 between the connection lines 22a and 22b to separate the source/drain electrodes 111 of the TFT unit 11, as shown in FIG. 1E; and
vii) applying a passivation layer 24 on the resulting structure of FIG. 1E, and using a sixth photo-masking and lithography procedure to pattern and etch the passivation layer 24 to expose the TAB contact window for the scan line, create a TAB contact window for the data line (not shown), and create an opening window A for the pixel electrode 20, as shown in FIG. 1F.
As known, the count of photo-masking and lithography steps directly affects not only the production cost but also the manufacturing time. Moreover, for each photo-masking and lithography step, the risks of mis-alignment and contamination may be involved so as to affect the production yield. The complicated 6-mask process mentioned as above thus results in relatively high cost and relatively low yield.
For current techniques, the above steps ix) and vii) can be combined to achieve a 5-mask process owing to the improvement on material. That is, all the TAB contact windows can be formed by a single masking and patterning step.
In order to further reduce the count of photo-masking and lithography steps, many efforts have been made to develop new processes. For example, U.S. Pat. Nos. 5,346,833 and 5,478,766 issued to Wu and Park et al., respectively, disclose 3 and/or 4-mask processes for making a TFTLCD, which are incorporated herein for reference. It is to be noted that the 3-mask process for each of Wu and Park et al. does not include the step of forming and patterning of a passivation layer. If a passivation layer is required to assure of satisfactory reliability, the count of photo-masking and lithography steps should be four.
Although Wu and Park et al. disclose the processes of reduced masks, the use of the ITO layer, which is integrally formed with the ITO pixel electrode, as the connection line between the TFT unit and the data line limits the area of the TFTLCD due to the high resistivity of ITO.
Therefore, an object of the present invention is to provide a reduced mask process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which the count of photo-masking and lithography steps can be reduced to three.
Another object of the present invention is to provide a BCE process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which the connection line between a TFT unit and a data line has a relatively low resistivity compared to the ITO connection line so as to be suitable for a large-area TFTLCD.
Another object of the present invention is to provide a simplified process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD), in which a part of data metal layer around a pixel electrode functions as a black matrix.
According to a first aspect of the present invention, a process for forming a thin film transistor (TFT) matrix for a liquid crystal display (LCD) includes steps of providing a substrate made of an insulating material; forming a first conductive layer on a first side of the substrate, and using a first masking and patterning procedure to remove a portion of the first conductive layer to define a scan line and a gate electrode of a TFT unit; successively forming an insulation layer, a semiconductor layer, a doped semiconductor layer, and a photoresist layer on the substrate with the scan line and the gate electrode; providing an exposing source from a second side of the substrate opposite to the first side by using the scan line and the gate electrode as shields to obtain an exposed area and an unexposed area; removing the photoresist layer, and the semiconductor layers of the exposed area so that the remaining portion of the semiconductor layers in the unexposed area has a specific shape similar to the shape of the scan line together with the gate electrode; successively forming a transparent conductive layer and a second conductive layer on the substrate, and using a second masking and patterning procedure to remove a portion of the transparent conductive layer and a portion of the second conductive layer to define a pixel electrode region and data and connection lines, respectively; removing another portion of the doped semiconductor layer with a remaining portion of the second conductive layer as shields to define source/drain regions; forming a passivation layer on the substrate, and using a third masking and patterning procedure to remove a portion of the passivation layer; and removing another portion of the second conductive layer with the patterned passivation layer as shields to expose the pixel electrode region.
When the exposing source is a light radiation, the insulating material is a light-transmitting material such as glass.
Preferably, each of the first and the second conductive layers is formed of chromium, molybdenum, tantalum, tantalum molybdenum, tungsten molybdenum, aluminum, aluminum silicide, copper, or a combination thereof.
Preferably, the insulation layer is formed of silicon nitride, silicon oxide, silicon oxynitride, tantalum oxide, aluminum oxide or a combination thereof.
Preferably, the etch stopper layer is formed of silicon nitride, silicon oxide, or silicon oxynitride.
Preferably, the semiconductor layer is formed of intrinsic amorphous silicon, micro-crystalline silicon or polysilicon, and the doped semiconductor layer is formed of highly doped amorphous silicon, highly doped micro-crystalline silicon or highly doped polysilicon.
Preferably, the transparent conductive layer is formed of indium tin oxide, indium zinc oxide or indium lead oxide.
Preferably, the passivation layer is formed of silicon nitride or silicon oxynitride.
Preferably, the third masking and patterning procedure additionally removes a portion of the semiconductor layer to define an isolation window.
Preferably, the third masking and patterning procedure additionally defines a plurality of TAB pad regions around the TFT matrix.
After the third masking and patterning procedure, it is preferred that a portion of the second conductive layer surrounding the pixel electrode remains as a black matrix.